To derive low-latency high-throughput FPGA designs out of a Process Network obtained from C-code, Compaan Design has developed a special HW accelerator wrapper. This wrapper consists of a communication part and a computation part. The communication part is derived from the parallelization done by the Compaan HotSpot parallelizer. The computation part is realized by a specific IP core. This IP core could for example be an Add operation, but also a more complex component that calculates a FFT (Fast Fourier Transform). The IP core could be hand written or is obtained from a C-to-VHDL compiler.

A schematic picture of the HW accelerator wrapper is shown above. This wrapper is unique IP developed and owned by Compaan Design. It is designed in such a way it can operate very well with (deep) pipelined IP cores. By overlapping calculations in a pipeline an enormous amount of parallelism can be exploited.

The output of the Compaan Code Generator for the HW accelerators is given in the form of VHDL files. This VHDL is self contained and self documented. This means that once Compaan Design has created the VHDL accelerators, the relationship with the original C-code is maintained. As a result, the VHDL code is human readable. Also, the VHDL can be processed by any commercial VHDL synthesize and implementation flow. Verilog output is also possible, if necessary.

The output of the Compaan Code Generator for the integration of multiple HW accelerators into a single system is expressed in the industrial IEEE standard 1685-200 (IP-XACT). This means that designs are portable and can be realized by any commercial VHDL synthesize and implementation flow that implements the IEEE standard.