Compaan Design is the technology leader in C-to-Dataflow conversion and its core technology is presented in the picture below. It shows a HotSpot expressed in C-code. This code is processed by the Compaan Parallelizer CompilerÂ into a Process Network. This is a complete mathematical procedure and as such makes sure that the behavior in C-code is also the behavior of the Process Network. The Process Network which captures the dataflow in the C-code in a natural way also expresses the C-code in terms of task, data and pipeline parallelism. Next step is to deploy the Process Network onto a compute architecture. This step is performed by the Compaan Code Generator. Currently two architectures are supported; generic multicore and FPGAs.
For Multicore, the Process Network described the threads necessary to partition the workload over multiple cores. Currently, two thread models are supported; the Pthread model and the Intel Threading Building Block® (TBB) model. Moving to other thread libraries can be done very easily.
For FPGAs, the Compaan technology has been extensively tested on Xilinx FPGAs using the Xilinx ISE®/EDK® products and Vivado®. The FPGAs from Altera are also supported. The data flow model naturally captured by the Process Network is mapped very efficiently on one or more FPGAs, which leads naturally to low-latency high-throughput design. The communication between the processes is expressed in streams that are mapped very efficient on FIFOs.