Compaan Design maintains a high level of Research & Development involvement to provide its customers with constant improvements. These improvements are in terms of the core Compaan technology, but also in terms of integration with the latest 3^rd party tools from EDA/FPGA vendors, new emerging communication standards, and tracking developments in FPGA technology in general.

As a technology innovator, Compaan Design is involved in a number of Europe-wide research projects. In these projects, we collaborate with industry partners and European research institutes. In these joint projects we seek innovative solutions to the challenges facing the Embedded and Multicore industry.

SoftSoC

SoftSoC is a CATRENE project that aims at solving the main SoC productivity bottleneck by providing Hardware Dependant Software (HDS) solutions to enable SoC designers to aggregate multiple HW IP with their associated HDS into efficient design. See www.softsoc.org for more information.

TSAR

TSAR is a CATRENE project that aims at the design and application of multi-core processor architectures targeting tera-flops performance. Topics are In-Network Cache Coherence Protocol on NoC-based architecture, Scalable Tera Bit/s IO design, Application Specific GALS NoC design, optimal Compilation for Multi-Core/Multi-Thread Processor. See http://www.catrene.org/web/projects/project_list.php for more information.

ASAM

ASAM is a research project in the framework of the European ARTEMIS Research Program and ARTEMIS Joint Undertaking - the public-private partnership for RD in Embedded Systems. ASAM targets a uniform process of automatic architecture synthesis and application mapping for heterogeneous multi-processor embedded systems based on adaptable and extendable ASIPs. It aims to define a new unified design methodology, as well as, related automated synthesis and prototyping tool-chains. The new design environment will allow rapid exploration of the high-level algorithm and architecture design spaces, as well as, an efficient automation of the final system synthesis, and in consequence, quick development of high-quality designs. See www.asam-project.org for more information.

COBRA

COBRA is a CATRENE project that focuses on Hardwired SoC architectures that suffer from a lack of flexibility regarding market evolution, resulting in an excessive design cycle time and increased cost. Furthermore, process variability is not yet well addressed for 32 nm and beyond. The objective of COBRA is to develop and experiment an open, flexible and high performance platform by substituting heterogeneous hardware/software subsystems by a regular array of processors. The platform will be driven by Telecom, Video and Multimedia benchmark applications and demonstrated on 32nm silicon with 3D stacking. See http://www.catrene.org/web/projects/project_list.php for more information.

HEAP

HEAP is an EU's seventh framework research project that addresses a key problem in the development process for current and future multi-core and multi-threaded architectures: the identification of a sufficient amount of thread-level parallelism (i.e. macro-parallelism) to exploit the available hardware, without imposing an excessive burden on the communication structure (often a shared memory or cache). See http://www.fp7-heap.eu/ for more information