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Compaan Hotspot Parallelization

Compaan Design's workflow guides step-by-step parallelization to improved energy efficiency and computational throughput.

Parallelism is exploited for streaming data and increased architecture utilization. Our exact dataflow analysis guarantees correctness and robustness of application execution. Code generation is heterogeneous and supports flexible HW/SW codesign.

It is a perfect solution for today's MPSoCs composed of DSPs, FPGAs and microprocessors. It easily retargets to customized processors and IP blocks.

 

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"Your legacy, our concern ...          
                  transition to multicore!"
 
Visit Compaan at DAC June 13-18 2010 at Booth N° 368 at the Anaheim Convention Center in Anaheim CA

Compaan Design releases HotSpot Parallelizer for ISO C. Product launch at DAC June 13-18 2010 on Compaan Design Booth N° 368 at the Anaheim Convention Center in Anaheim CA.

 
Visit Compaan on ACE booth 2301 at ESC April 26 - 29, 2010 in San Jose

Compaan Design will join OEM-partner ACE at the ACE booth 2301 on the Embedded Systems Conference from April 26 - 29, 2010 at the McEnery Convention Center in San Jose CA.

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Latest News
    Compaan Design featured at EngineeringTV.com
    Watch Joe Desposito of Electronic Design interview Compaan Design at DAC 2010.
    Compaan Design releases HotSpot Parallelizer for C

    Compaan Design Press Release


    Compaan Design releases HotSpot Parallelizer for ISO C; Philips Healthcare reports VHDL productivity boosts.

    Compaan Design speeds up JPEG 2000

    Compaan Design realizes near-linear speed-up on JPEG 2000 benchmark.

 
 
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